The present inventive concepts relate to sense amplifiers for resistive type memory circuits, and more particularly to current sense amplifiers.
Resistive type memories encompass a new generation of non-volatile memory and are expected to become more prevalent in the marketplace. Resistive type memories can include, for example, spin transfer torque (STT) magnetoresistive random-access memory (MRAM), MRAM (of the non-STT variety), memristor RAM, ReRAM, CBRAM, and the like.
FIG. 1A is a circuit diagram of a sense amplifier according to the prior art. Referring to FIG. 1A, a latch circuit is configured by MOS transistors M1, M2, M3, and M4. MOS transistors M5 and M6 correspond to the read current source IR1 and the reference current source IR2, respectively. A sense amplifier is configured by MOS transistors M7 and M8. An operation of the read circuit 15 includes (a) a pre-charge mode, (b) an amplification mode, and (c) a latch+rewrite mode. The modes are described below with reference to FIGS. 1B-1D. In an initial state, control signals φ1, φ2, and φ3 from a switch controller are set at a low (“L”) state.
FIGS. 1B-1D are equivalent circuit diagrams of the circuit diagram of FIG. 1A associated with different stages of operation, in accordance with the prior art.
FIG. 1B shows an equivalent circuit in the pre-charge mode. The control signal φ2 is set at a high (“H”) state to start pre-charging a read current path. A pre-charge current flows from the pre-charge transistors M5 and M6 (PMOS transistors) to the MRAM cell 13 and the reference cell 13′ through the cross-coupled transistors M3 and M4 (NMOS transistors) serving as a part of the latch circuit and clamp transistors M11 and M12 (NMOS transistors) of FIG. 1A. In the pre-charge mode and a stable state, read data Out and /Out are set at a voltage close to a power supply voltage VSS by the pre-charge transistors M5 and M6 and an equalize transistor Meq (PMOS transistor). Therefore, the transistors M1 and M2 are in off states, and the latch circuit including transistors M1 to M4 does not operate.
FIG. 1C shows an equivalent circuit in an amplification mode. The control signal φ1 is set at “H”, and the transistors M5, M6, and Meq are turned off. The data Out and /Out decrease from a power supply voltage VDD by threshold voltages of the transistors M1 and M2, amplification by positive feedback of the latch circuit including the MOS transistors M1 to M4, and the data Out and /Out are determined. At this time, the read current path is identical with a drive current path of the latch circuit, and the control signal φ1 goes to “H”, so that the operation continuously is shifted from the pre-charge mode to the amplification mode. Although present in the overall circuit during the amplification mode, the clamp transistors M11 and M12 are not shown in FIG. 1C.
FIG. 1D shows an equivalent circuit in an latch+rewrite mode. As shown in FIG. 1D, when a voltage difference between outputs Out and /Out is sufficiently large, the control signal φ3 is set at “H” to turn the boost transistors M7 and M8 on, and amplification of the latch circuit including the transistors M1 to M4 is accelerated. When an output from the latch circuit, i.e., the data Out and /Out are determined, rewriting is performed.
Conventional sense amplifier technology used in resistive type memories can experience problems as the power supply voltages are decreasing over time. As the size of memory cells decreases and the density of memory devices increases over time, the power supply voltages used to supply power to the memory cells and associated control logic is also decreased. Whereas in times past the power supply voltage for a memory circuit may have been 5 Volts (V) or 3.3 V, for example, today a power supply voltage may supply voltages around 1.2 V or 1.3 V. Such low power supply voltages can cause voltage headroom problems in conventional sense amplifier circuitry as the saturation voltage of a transistor may not scale down proportionally to the supply voltage.
Problems associated with available voltage headroom within sense amplifiers are aggravated when too many transistors are configured in stacked structures, which can cause undesirable operation in one or more of the transistors. For example, a transistor that would be more effective if it operated in a saturation region mode in certain phases of the sense amplifier operation, may in reality be operating in a triode or linear region mode, thereby causing disadvantages in sense amplifier operation.
Other unique challenges are presented when attempting to develop sense amplifier technology associated with resistive type memories. For example, in an MRAM type memory cell, a destructive read or “read disturb” problem can occur if the sense amplifier causes excess current to flow through an MRAM memory cell when attempting to sense whether a “1” or a “0” is stored in the memory cell. In other words, the value of the memory cell can accidentally be switched from a “1” to a “0” or vice versa.
One approach to avoid the read disturb problem is for the sense amplifier to reduce the read current. However, unintended side effects of this approach can include slower response times, a reduction in the output signal level, a reduction in the data read rate, and higher susceptibility to unwanted electromagnetic noise and other disturbances. Such performance degradation is undesirable. Moreover, such electromagnetic noise itself can be disruptive to the data stored in the cell or to the sense amplifier output signals.
It would be desirable to provide a current sense amplifier circuit for resistive type memories, which provides fast response times, strong noise immunity, low voltage operation, larger voltage headroom, and fewer sense errors.